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Section 28 Sampling Rate Converter
R01UH0134EJ0400 Rev. 4.00 Page 1645 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
28.2.4 Output Data Control Register (SRCODCTRL)
SRCODCTRL is a 16-bit readable/writable register that specifies whether to exchange the
channels for the output data, specifies the endian format of output data, enables/disables the
interrupt requests, and specifies the triggering number of data units.
1514131211109876543210
Bit:
Initial value:
R/W:
0000000000000000
RRRRRR/WR/WR/WRRRRRRR/WR/W
⎯⎯⎯⎯⎯
OCH OED OEN
⎯⎯
-
⎯⎯⎯⎯
OFTRG[1:0]
Bit Bit Name
Initial
Value
R/W Description
15 to 11 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
10 OCH 0 R/W Output Data Channel Exchange
Specifies whether to exchange the channels for the
output data register (SRCOD). When processing
monaural data, do not set this bit to 1.
0: Does not exchange the channels (the same order
as data input)
1: Exchanges the channels (the opposite order from
data input)
Note: For channel 1, this bit is reserved and always
read as 0. The write value should always be 0.