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Section 7 Interrupt Controller
R01UH0134EJ0400 Rev. 4.00 Page 197 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
F
2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc m1 m2 m3
3 Icyc + m1 + m2
IRQ
Instruction (instruction replacing
interrupt exception handling)
m1:
m2:
m3:
F:
D:
E:
M:
First instruction in interrupt exception
service routine
Interrupt acceptance
DEEMM
M
FD
E
[Legend]
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Instruction fetch. Instruction is fetched from memory in which program is stored.
Instruction decoding. Fetched instruction is decoded.
Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding.
Memory access. Memory data access is performed.
Figure 7.4 Example of Pipeline Operation when IRQ Interrupt is Accepted
(No Register Banking)