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Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00 Page 1587 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.10 Video Base Address Register (VIDEO_BASEADR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
151413121110987654321
0
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
VIDEO_BASEADR[15:0]
VIDEO_BASEADR[31:16]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value
R/W Description
31 to 0 VIDEO_
BASEADR
[31:0]
H'00000000 R/W These bits specify the base address of the
destination where video data is to be written to.
According to the BURST_MODE_MAIN bit setting
in the VIDEO_MODE register, the lower bits should
be set as follows.
In 16-byte burst transfer: The lower four bits should
always be 0000.
In 128-byte burst transfer: The lower seven bits
should always be 000_0000.