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Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00 Page 561 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(m) Counter Clearing by Another Channel
In complementary PWM mode, by setting a mode for synchronization with another channel by
means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits
CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4,
and TCNTS cleared by another channel.
Figure 11.55 illustrates the operation.
Use of this function enables counter clearing and restarting to be performed by means of an
external signal.
TGRA_3
TCDR
TDDR
H'0000
Channel 1
Input capture A
TCNT_1
TCNT_3
TCNT_4
TCNTS
Synchronous counter clearing by channel 1 input capture A
Figure 11.55 Counter Clearing Synchronized with Another Channel