Filter
Top Products
Section 33 Power-Down Modes
R01UH0134EJ0400 Rev. 4.00 Page 1807 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
33.3.2 Software Standby Mode
(1) Transition to Software Standby Mode
The LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit and DEEP bit in STBCR1 are 1 and 0 respectively. In
software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
The clock output from the CKIO pin also stops.
The contents of the CPU and cache registers remain unchanged. Some registers of on-chip
peripheral modules are, however, initialized. As for the states of on-chip peripheral module
registers in software standby mode, see section 36.3, Register States in Each Operating Mode.
The CPU takes one cycle to finish writing to STBCR1, and then executes processing for the next
instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP
instruction after reading STBCR1 to have the values written to STBCR1 by the CPU to be
definitely reflected in the SLEEP instruction.
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the timer control register of the watchdog timer (WTCSR) to 0 to stop the
watchdog time.
2. Set the timer counter of the watchdog timer (WTCNT) to 0 and the CKS[2:0] bits in WTCSR
to appropriate values to secure the specified oscillation settling time.
3. After setting the STBY and DEEP bits in STBCR1 to 1 and 0 respectively, read STBCR1.
Then, execute a SLEEP instruction.