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Section 15 Serial Communication Interface with FIFO
R01UH0134EJ0400 Rev. 4.00 Page 739 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
7, 6 RTRG[1:0] 00 R/W Receive FIFO Data Trigger
Set the quantity of receive data which sets the receive
data full (RDF) flag in the serial status register
(SCFSR). The RDF flag is set to 1 when the quantity
of receive data stored in the receive FIFO register
(SCFRDR) is increased more than the set trigger
number shown below.
Asynchronous mode Clock synchronous mode
00: 1
01: 4
10: 8
11: 14
00: 1
01: 2
10: 8
11: 14
Note: In clock synchronous mode, to transfer the
receive data using the direct memory access
controller, set the receive trigger number to 1. If
set to other than 1, CPU must read the receive
data left in SCFRDR.
5, 4 TTRG[1:0] 00 R/W Transmit FIFO Data Trigger
Set the quantity of remaining transmit data which sets the
transmit FIFO data register empty (TDFE) flag in the
serial status register (SCFSR). The TDFE flag is set to 1
when the quantity of transmit data in the transmit FIFO
data register (SCFTDR) becomes less than the set trigger
number shown below.
00: 8 (8)*
01: 4 (12)*
10: 2 (14)*
11: 0 (16)*
Note: * Values in parentheses mean the number of
empty bytes in SCFTDR when the TDFE flag
is set to 1.