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Page xiv of xl R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
Section 7 Interrupt Controller ............................................................................ 157
7.1 Features ............................................................................................................................. 157
7.2 Input/Output Pins .............................................................................................................. 159
7.3 Register Descriptions ........................................................................................................ 160
7.3.1 Interrupt Priority Registers 01, 02, 05 to 22
(IPR01, IPR02, IPR05 to IPR22) ..................................................................... 162
7.3.2 Interrupt Control Register 0 (ICR0) .................................................................. 164
7.3.3 Interrupt Control Register 1 (ICR1) .................................................................. 166
7.3.4 Interrupt Control Register 2 (ICR2) .................................................................. 167
7.3.5 IRQ Interrupt Request Register (IRQRR) ......................................................... 168
7.3.6 PINT Interrupt Enable Register (PINTER) ....................................................... 169
7.3.7 PINT Interrupt Request Register (PIRR) .......................................................... 170
7.3.8 Bank Control Register (IBCR) .......................................................................... 171
7.3.9 Bank Number Register (IBNR) ........................................................................ 172
7.4 Interrupt Sources ............................................................................................................... 173
7.4.1 NMI Interrupt .................................................................................................... 173
7.4.2 User Debugging Interface Interrupt .................................................................. 174
7.4.3 IRQ Interrupts ................................................................................................... 174
7.4.4 PINT Interrupts ................................................................................................. 175
7.4.5 On-Chip Peripheral Module Interrupts ............................................................. 176
7.5 Interrupt Exception Handling Vector Table and Priority .................................................. 177
7.6 Operation .......................................................................................................................... 191
7.6.1 Interrupt Operation Sequence ........................................................................... 191
7.6.2 Stack after Interrupt Exception Handling ......................................................... 194
7.7 Interrupt Response Time ................................................................................................... 195
7.8 Register Banks .................................................................................................................. 201
7.8.1 Banked Register and Input/Output of Banks .................................................... 202
7.8.2 Bank Save and Restore Operations ................................................................... 202
7.8.3 Save and Restore Operations after Saving to All Banks ................................... 204
7.8.4 Register Bank Exception .................................................................................. 205
7.8.5 Register Bank Error Exception Handling ......................................................... 205
7.9 Data Transfer with Interrupt Request Signals ................................................................... 206
7.9.1 Handling Interrupt Request Signals as Sources for
CPU Interrupt but Not Direct Memory Access Controller Activating .............. 207
7.9.2 Handling Interrupt Request Signals as Sources for
Activating Direct Memory Access Controller but Not CPU Interrupt .............. 207
7.10 Usage Note ....................................................................................................................... 208
7.10.1 Timing to Clear an Interrupt Source ................................................................. 208