Filter
Top Products
Section 26 USB 2.0 Host/Function Module
Page 1484 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(c) When the BRDYM bit is 1 and the BFRE bit is 0
With these settings, the PIPEBRDY values are linked to the BSTS bit settings for each pipe. In
other words, the BRDY interrupt status bits (PIPEBRDY) are set to 1 or 0 by this module
depending on the FIFO buffer status.
(i) For the pipe in the transmitting direction:
The BRDY interrupt status bits are set to 1 when the FIFO buffer is write-enabled and are set to 0
when write-disabled.
However, the BRDY interrupt is not generated if the DCP in the transmitting direction is write-
enabled.
(ii) For the pipe in the receiving direction:
The BRDY interrupt status bits are set to 1 when the FIFO buffer is read-enabled and are set to 0
when all the data have been read (read-disabled).
When a zero-length packet is received when the FIFO buffer is empty, the pertinent bit is set to 1
and the BRDY interrupt is continuously generated until BCLR = 1 is written. With this setting, the
PIPEBRDY bit cannot be cleared to 0. When BRDYM is set to 1, all of the BFRE bits (for all
pipes) should be cleared to 0.