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Section 37 Electrical Characteristics
R01UH0134EJ0400 Rev. 4.00 Page 1987 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
t
AD1
t
AD1
T1
t
RWD1
t
RSD
t
WED1
t
WED1
t
WED1
t
RDS1
t
RDS1
t
AS
t
RSD
t
RSD
t
AH
t
RSD
t
WDH4
t
WDH4
t
WED1
t
AH
t
AH
t
CSD1
t
WDD1
t
WDH1
t
WDH1
t
WDD1
t
BSD
t
BSD
t
DACD
t
DACD
t
DACD
t
DACD
t
BSD
t
BSD
t
RWD1
t
RWD1
t
RWD1
t
CSD1
t
CSD1
t
CSD1
t
AS
t
CS
t
CS
t
AD1
t
AD1
Tw T2 Ta w T1 Tw T2 Taw
DACKn
TENDn*
Note: * The waveform for DACKn and TENDn is when active low is specified.
A25 to A0
D15 to D0
CSn
RD/WR
RD
WAIT
D15 to D0
WEn
BS
CKIO
t
WTH
t
WTS
t
WTH
t
WTS
ReadWrite
t
RDH1
t
RDH1
Figure 37.12 Basic Bus Timing for Normal Space
(One Software Wait Cycle, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle)