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R01UH0134EJ0400 Rev. 4.00 Page 2089 of 2108
Sep 24, 2014
Item Page Revision (See Manual for Details)
37.4.3 Bus Timing
Figure 37.11 Basic Bus
Timing for Normal Space
(One Software Wait Cycle,
One External Wait Cycle)
1986 Figure replaced and title amended
Figure 37.13 MPX-I/O
Interface Bus Cycle
(Three Address Cycles, One
Software Wait Cycle, One
External Wait Cycle)
1988 Figure amended
Ta 1 Ta2 Ta 3 T1 Tw Twx T2
CKIO
Figure 37.14 Bus Cycle of
SRAM with Byte Selection
(SW = 1 Cycle, HW = 1
Cycle, One Asynchronous
External Wait Cycle, BAS = 0
(Write Cycle UB/LB Control))
1989 Figure amended
Read
Write
t
RSD
t
RSD
t
RDS1
t
WDD1
t
WDH1
t
RDH1
RD
D15 to D0
D15 to D0
RD/WR
RD/WR
t
RWD1
t
RWD1
Figure 37.15 Bus Cycle of
SRAM with Byte Selection
(SW = 1 Cycle, HW = 1
Cycle, One Asynchronous
External Wait Cycle, BAS = 1
(Write Cycle WE Control))
1990 Figure amended
t
RSD
t
RSD
t
RDS1
t
RWD1
t
WDD1
t
RWD1
t
RWD1
t
WDH1
t
RDH1
RD
D15 to D0
D15 to D0
RD/WR
RD/WR
t
RWD1
Read
Write
Figure 37.16 Burst ROM
Read Cycle (One Software
Wait Cycle, One
Asynchronous External Burst
Wait Cycle, Two Burst)
1991 Figure amended
t
RDS3
D15 to D0
t
RDS3