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Page 2090 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
Item Page Revision (See Manual for Details)
37.4.3 Bus Timing
Figure 37.17 Synchronous
DRAM Single Read Bus
Cycle (Auto Precharge, CAS
Latency 2, WTRCD = 0
Cycle, WTRP = 0 Cycle)
1992 Figure amended
t
RDH2
t
RDS2
t
RASD1
t
RASD1
t
CASD1
t
CASD1
t
DQMD1
t
DQMD1
D15 to D0
RAS
CAS
DQMxx
Figure 37.18 Synchronous
DRAM Single Read Bus
Cycle (Auto Precharge, CAS
Latency 2, WTRCD = 1
Cycle, WTRP = 1 Cycle)
1993 Figure amended
t
RDH2
t
RDS2
D15 to D0
t
RASD1
t
RASD1
RAS
t
CASD1
t
CASD1
CAS
t
DQMD1
t
DQMD1
DQMxx
Figure 37.19 Synchronous
DRAM Burst Read Bus Cycle
(Four Read Cycles) (Auto
Precharge, CAS Latency 2,
WTRCD = 0 Cycle, WTRP =
1 Cycle)
1994 Figure amended
t
RDH2
t
RDS2
D15 to D0
t
RASD1
t
RASD1
RAS
t
CASD1
t
CASD1
CAS
t
DQMD1
t
DQMD1
DQMxx
t
RDH2
t
RDS2
Figure 37.20 Synchronous
DRAM Burst Read Bus Cycle
(Four Read Cycles) (Auto
Precharge, CAS Latency 2,
WTRCD = 1 Cycle, WTRP =
0 Cycle)
1995 Figure amended
t
RDH2
t
RDS2
D15 to D0
t
RASD1
t
RASD1
RAS
t
CASD1
t
CASD1
CAS
t
DQMD1
t
DQMD1
DQMxx
t
RDH2
t
RDS2