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Section 2 CPU
Page 68 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Instruction Formats
Source
Operand
Destination
Operand
Example
i format
xxxxxxxx iiii
15 0
iiii
iiiiiiii: Immediate Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
iiiiiiii: Immediate R0 (Register direct) AND #imm,R0
iiiiiiii: Immediate TRAPA #imm
ni format
nnnn
iiii
xxxx
15 0
iiii
iiiiiiii: Immediate nnnn: Register direct ADD #imm,Rn
ni3 format
xxxx
nnnn
xxxx
15 0
iiix
nnnn: Register direct
iii: Immediate
BLD #imm3,Rn
nnnn: Register direct
iii: Immediate
BST #imm3,Rn
ni20 format
iiii iiii iiiiiiii
15
0
xxxx iiii xxxxnnnn
32
16
iiiiiiiiiiiiiiiiiiii:
Immediate
nnnn: Register direct MOVI20
#imm20, Rn
nid format
xxxx dddd dddddddd
15
0
xxxx xiii xxxxnnnn
32
16
nnnndddddddddddd:
Register indirect with
displacement
iii: Immediate
BLD.B
#imm3,@(disp12,Rn)
nnnndddddddddddd:
Register indirect with
displacement
iii: Immediate
BST.B
#imm3,@(disp12,Rn)
Note: * In multiply-and-accumulate instructions, nnnn is the source register.