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R01UH0134EJ0400 Rev. 4.00 Page xxxv of xl
Sep 24, 2014
28.2.5 Control Register (SRCCTRL) ......................................................................... 1647
28.2.6 Status Register (SRCSTAT) ........................................................................... 1653
28.3 Operation ........................................................................................................................ 1658
28.3.1 Initial Setting................................................................................................... 1658
28.3.2 Data Input ....................................................................................................... 1659
28.3.3 Data Output ..................................................................................................... 1661
28.4 Interrupts ......................................................................................................................... 1663
28.5 Usage Notes .................................................................................................................... 1664
28.5.1 Notes on Accessing Registers ......................................................................... 1664
28.5.2 Notes on Flush Processing .............................................................................. 1664
28.5.3 Notes on Using Two Channels at the Same Time ........................................... 1665
Section 29 SD Host Interface ........................................................................... 1667
Section 30 Decompression Unit ...................................................................... 1669
Section 31 On-Chip RAM ............................................................................... 1671
31.1 Features ........................................................................................................................... 1671
31.2 Usage Notes .................................................................................................................... 1675
31.2.1 Page Conflict................................................................................................... 1675
31.2.2 RAME and RAMWE Bits .............................................................................. 1675
31.2.3 Data Retention ................................................................................................ 1676
Section 32 General Purpose I/O Ports ............................................................. 1677
32.1 Features ........................................................................................................................... 1677
32.2 Register Descriptions ...................................................................................................... 1686
32.2.1 Port A I/O Register 0 (PAIOR0) ..................................................................... 1689
32.2.2 Port A Data Registers 1, 0 (PADR1, PADR0) ................................................ 1689
32.2.3 Port A Port Register 0 (PAPR0) ..................................................................... 1691
32.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5) ...................................... 1691
32.2.5 Port B I/O Registers 0, 1 (PBIOR0, PBIOR1) ................................................ 1701
32.2.6 Port B Data Registers 0, 1 (PBDR0, PBDR1) ................................................ 1702
32.2.7 Port B Port Registers 0, 1 (PBPR0, PBPR1) ................................................... 1704
32.2.8 Port C Control Registers 0 to 2 (PCCR0 to PCCR2) ...................................... 1706
32.2.9 Port C I/O Register 0 (PCIOR0) ..................................................................... 1709
32.2.10 Port C Data Register 0 (PCDR0) .................................................................... 1710
32.2.11 Port C Port Register 0 (PCPR0) ...................................................................... 1712
32.2.12 Port D Control Register 0 to 3 (PDCR0 to PDCR3) ....................................... 1713
32.2.13 Port D I/O Register 0 (PDIOR0) ..................................................................... 1719
32.2.14 Port D Port Registers 0 (PDDR0) ................................................................... 1720