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Section 8 Cache
R01UH0134EJ0400 Rev. 4.00 Page 213 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
31 to 12
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
11 ICF 0 R/W Instruction Cache Flush
Writing 1 flushes all instruction cache entries (clears the
V and LRU bits of all instruction cache entries to 0).
Always reads 0. Write-back to the external memory or
the large-capacity on-chip RAM is not performed when
the instruction cache is flushed.
10, 9
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
8 ICE 0 R/W Instruction Cache Enable
Indicates whether the instruction cache function is
enabled/disabled.
0: Instruction cache disable
1: Instruction cache enable
7 to 4
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
3 OCF 0 R/W Operand Cache Flush
Writing 1 flushes all operand cache entries (clears the
V, U, and LRU bits of all operand cache entries to 0).
Always reads 0. Write-back to the external memory or
the large-capacity on-chip RAM is not performed when
the operand cache is flushed.
2
0 R Reserved
This bit is always read as 0. The write value should
always be 0.
1 WT 0 R/W Write Through
Selects write-back mode or write-through mode.
0: Write-back mode
1: Write-through mode
0 OCE 0 R/W Operand Cache Enable
Indicates whether the operand cache function is
enabled/disabled.
0: Operand cache disable
1: Operand cache enable