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Section 27 Video Display Controller 3
Page 1552 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
27.5 Input Video Interface
27.5.1 BT.601 Video Input
The DV_VSYNC and DV_HSYNC signals conforming to BT.601 should be input with the timing
shown in figure 27.2. The timing for sampling these signal inputs can be selected as either the
rising or falling edge of the DV_CLK. Negative polarity is also supported. The field type is
determined according to the DV_VSYNC and DV_HSYNC timing.
DV_CLK
DV_VSYNC
DV_HSYNC
DV_DATA_7 to
DV _DATA _0
DV_VSYNC
DV_HSYNC
DV_DATA_7 to
DV _DATA _0
TOP field
BOTTOM field
Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3
1/2H
Figure 27.2 BT.601 Input Interface Signals