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R01UH0134EJ0400 Rev. 4.00 Page 2095 of 2108
Sep 24, 2014
Item Page Revision (See Manual for Details)
37.4.8 Renesas Serial
Peripheral Interface Timing
Figure 37.47 Clock Timing
2020 Figure replaced
Figure 37.48 Transmission
and Reception Timing
(Master, CPHA = 0)
Figure 37.49 Transmission
and Reception Timing
(Master, CPHA = 1)
2021
Figure 37.50 Transmission
and Reception Timing
(Slave, CPHA = 0)
Figure 37.51 Transmission
and Reception Timing
(Slave, CPHA = 1)
2022
37.4.9 I
2
C Bus Interface 3
Timing
Table 37.13 (1) I
2
C Bus
Interface 3 Timing I
2
C Bus
Format
2023 Table and title amended
erugiF tinU .xaM .niM lobmyS metI
t emit elcyc tupni LCS
SCL
12 t
pcyc
*
1
+ 600 ⎯ ns
Figure 37.52
(1)
SCL input high pulse width t
SCLH
3 t
pcyc
*
1
+ 300 ⎯ ns
Figure 37.52 (1)
Input/Output Timing
Figure title amended
Table 37.13 (2) I
2
C Bus
Interface 3 Timing Clock
Synchronized Serial Format
2024 Table added
Figure 37.52 (2) Clock
Input/Output Timing
Figure added
Figure 37.52 (3)
Transmission and Reception
Timing