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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1041 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit 12 — TCMR2 compare match enable: When this bit is set, IRR11 is set by TCMR2
compare match.
Bit12 TTCR0 12 Description
0 IRR11 isn't set by TCMR2 compare match (initial value)
1 IRR11 is set by TCMR2 compare match
Bit 11 — TCMR1 compare match enable: When this bit is set, IRR15 is set by TCMR1
compare match.
Bit11 TTCR0 11 Description
0 IRR15 isn't set by TCMR1 compare match (initial value)
1 IRR15 is set by TCMR1 compare match
Bit 10 — TCMR0 compare match enable: When this bit is set, IRR14 is set by TCMR0
compare match.
Bit10 TTCR0 10 Description
0 IRR14 isn't set by TCMR0 compare match (initial value)
1 IRR14 is set by TCMR0 compare match
Bits 9 to 7: Reserved. The written value should always be '0' and the returned value is '0'.
Bit 6 — Timer Clear-Set Control by TCMR0: Specifies if the Timer is to be cleared and set to
H'0000 when the TCMR0 matches to the TCNTR. Please note that the TCMR0 is also capable to
generate an interrupt signal to the CPU via IRR14.
Note: If this module is working in TTCAN mode (CMAX isn't 3'b111), TTCR0 bit6 has to be '0'
to avoid clearing Local Time.
Bit6: TTCR0 6 Description
0 Timer is not cleared by the TCMR0 (initial value)
1 Timer is cleared by the TCMR0