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Section 9 Bus State Controller
Page 256 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
read access wait cycles)
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CS4 assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles