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Section 19 Serial I/O with FIFO
Page 942 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
19.3 Register Descriptions
Table 19.2 shows the register configuration.
Table 19.2 Register Configuration
Register Name Abbreviation R/W Initial Value Address
Access
Size
Mode register SIMDR R/W H'8000 H'FFFF4800 16
Clock select register SISCR R/W H'8000 H'FFFF4802 16
Transmit data assign register SITDAR R/W H'0000 H'FFFF4804 16
Receive data assign register SIRDAR R/W H'0000 H'FFFF4806 16
Control register SICTR R/W H'0000 H'FFFF480C 16
FIFO control register SIFCTR R/W* H'1000 H'FFFF4810 16
Status register SISTR R/W* H'0000 H'FFFF4814 16
Interrupt enable register SIIER R/W H'0000 H'FFFF4816 16
Transmit data register SITDR W Undefined H'FFFF4820 8, 16, 32
Receive data register SIRDR R Undefined H'FFFF4824 8, 16, 32
Note: * This register has readable/writable bits and read-only bits. For details, see descriptions
for each register.