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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1035 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
RXPR0
1514131211109876543210Bit:
Initial value:
R/W:
0000000000000000
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
RXPR0[15:0]
Note: * Only when writing a '1' to clear.
Bit 15 to 0 — Configurable receive mailbox locations corresponding to each mailbox position
from 15 to 0 respectively.
Bit[15:0]: RXPR0 Description
0 [Clearing Condition] Writing '1' (Initial value)
1 Corresponding Mailbox received a CAN Data Frame
[Setting Condition]
Completion of Data Frame receive on corresponding mailbox
(6) Remote Frame Receive Pending Register (RFPR1, RFPR0)
The RFPR1 and RFPR0 are 16-bit read/conditionally-write registers. The RFPR is a register that
contains the received Remote Frame pending flags associated with the configured Receive
Mailboxes. When a CAN Remote Frame is successfully stored in a receive mailbox the
corresponding bit is set in the RFPR. The bit may be cleared by writing a '1' to the corresponding
bit position. Writing a '0' has no effect. In effect there is a bit position for all mailboxes. However,
the bit may only be set if the mailbox is configured by its MBC (Mailbox Configuration) to
receive Remote Frames. When a RFPR bit is set, it also sets IRR2 (Remote Frame Receive
Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask Register) is not set, and the interrupt signal
is generated if IMR2 is not set. Please note that these bits are only set by receiving Remote Frames
and not by receiving Data frames.
RFPR1
1514131211109876543210Bit:
Initial value:
R/W:
0000000000000000
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
RFPR1[15:0]
Note: * Only when writing a '1' to clear.