Filter
Top Products
Section 9 Bus State Controller
Page 258 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
CS5WCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
R R R R R R R R R R R/W R/W R R/W R/W R/W
0000010100000000
R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
----------SZSEL
MPXW/
BAS
- WW[2:0]
- - - SW[1:0] WR[3:0] WM - - - - HW[1:0]
Bit Bit Name
Initial
Value R/W Description
31 to 22 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
21 SZSEL 0 R/W MPX-I/O Interface Bus Width Specification
Specifies an address to select the bus width when the
BSZ[1:0] of CS5BCR are specified as 11. This bit is
valid only when area 5 is specified as MPX-I/O.
0: Selects the bus width by address A14
1: Selects the bus width by address A21
The relationship between the SZSEL bit and bus
width selected by A14 or A21 are summarized below.
SZSEL A14 A21 Bus Width
0 0 Not affected 8 bits
0 1 Not affected 16 bits
1 Not affected 0 8 bits
1 Not affected 1 16 bits
20 MPXW 0 R/W MPX-I/O Interface Address Wait
This bit setting is valid only when area 5 is specified
as MPX-I/O. Specifies the address cycle insertion wait
for MPX-I/O interface.
0: Inserts no wait cycle
1: Inserts 1 wait cycle