Filter
Top Products
Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 411 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Choose to detect DREQ by either the edge or level of the signal input with the DL and DS bits in
CHCR_0 and CHCR_1*
2
as shown in table 10.5. The source of the transfer request does not have
to be the data transfer source or destination. When DREQ is detected by a rising/falling edge and
DMA transfer is performed in burst mode, the transfer continues until DMATCR reaches 0 by one
DMA transfer request. In cycle steal mode, one DMA transfer is performed by one request.
Notes: 1. Only DREQ0 can be used in the SH7262 Group.
2. Only CHCR_0 can be used in the SH7262 Group.
Table 10.5 Selecting External Request Detection with DL and DS Bits
CHCR
Detection of External Request DL Bit DS Bit
0 0 Low-level detection
1 Falling-edge detection
1 0 High-level detection
1 Rising-edge detection
When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive
period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again
enters the request accept enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
Overrun 0: Transfer is terminated after the same number of transfer has been performed as
requests.
Overrun 1: Transfer is terminated after transfers have been performed for (the number of
requests plus 1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 10.6 Selecting External Request Detection with DO Bit
CHCR
External Request DO Bit
0 Overrun 0
1 Overrun 1