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Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00 Page 1597 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
MSB 32 bits
16 bits
RGB0 RGB1
LSB
31
15
0
0
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Note: The image is displayed in the order of pixels (RGB0 -> RGB1) from left to right.
Big Endian
MSB 32 bits
16 bits
RGB1
I bus
I bus RGB0
LSB
31
15
0
0
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Little Endian
α
Figure 27.19 Descriptions of Endian