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Section 11 Multi-Function Timer Pulse Unit 2
Page 550 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(g) PWM Cycle Setting
In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which
the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set.
The settings should be made so as to achieve the following relationship between these two
registers:
With dead time: TGRA_3 set value = TCDR set value + TDDR set value
TCDR set value > two times TDDR + 2
Without dead time: TGRA_3 set value = TCDR set value + 1
TCDR set value > 4
The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and
TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and
TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode
register (TMDR).
The updated PWM cycle is reflected from the next cycle when the data update is performed at the
crest, and from the current cycle when performed in the trough. Figure 11.42 illustrates the
operation when the PWM cycle is updated at the crest.
See (h) Register Data Updating, for the method of updating the data in each buffer register.
Counter value
TGRC_3
update
TGRA_3
update
TGRA_3
TCNT_3
TCNT_4
Time
Figure 11.42 Example of PWM Cycle Updating