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Page 2092 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
Item Page Revision (See Manual for Details)
37.4.3 Bus Timing
Figure 37.24 Synchronous
DRAM Burst Write Bus Cycle
(Four Write Cycles) (Auto
Precharge, WTRCD = 1
Cycle, TRWL = 1 Cycle)
1999 Figure amended
D15 to D0
t
RASD1
t
RASD1
RAS
t
CASD1
t
CASD1
CAS
t
DQMD1
t
DQMD1
DQMxx
t
WDH2
t
WDD2
t
WDH2
t
WDD2
Figure 37.25 Synchronous
DRAM Burst Read Bus Cycle
(Four Read Cycles) (Bank
Active Mode: ACT + READ
Commands, CAS Latency 2,
WTRCD = 0 Cycle)
2000 Figure amended
D15 to D0
t
RASD1
t
RASD1
RAS
t
CASD1
t
CASD1
CAS
t
DQMD1
t
DQMD1
DQMxx
t
RDH2
t
RDS2
t
RDH2
t
RDS2
Figure 37.26 Synchronous
DRAM Burst Read Bus Cycle
(Four Read Cycles) (Bank
Active Mode: READ
Command, Same Row
Address, CAS Latency 2,
WTRCD = 0 Cycle)
2001 Figure amended
D15 to D0
t
RASD1
RAS
t
CASD1
t
CASD1
CAS
t
DQMD1
t
DQMD1
DQMxx
t
RDH2
t
RDS2
t
RDH2
t
RDS2
Figure 37.27 Synchronous
DRAM Burst Read Bus Cycle
(Four Read Cycles) (Bank
Active Mode: PRE + ACT +
READ Commands, Different
Row Addresses, CAS
Latency 2, WTRCD = 0
Cycle)
2002 Figure amended
D15 to D0
t
RASD1
t
RASD1
t
RASD1
t
RASD1
RAS
t
CASD1
t
CASD1
CAS
t
DQMD1
t
DQMD1
DQMxx
t
RDH2
t
RDS2
t
RDH2
t
RDS2