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Section 35 Motor Control PWM Timer
Page 1840 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
35.3.7 PWM Buffer Transfer Control Register (PWBTCR)
PWBTCR enables or disables the data transfer from buffer register to duty register with the
compare match of PWM counter and PWM cycle register.
7
BTC2G
0
R/W
6
BTC2E
0
R/W
5
BTC2C
0
R/W
4
BTC2A
0
R/W
3
BTC1G
0
R/W
0
BTC1A
0
R/W
2
BTC1E
0
R/W
1
BTC1C
0
R/W
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
Initial
Value R/W Description
7 BTC2G 0 R/W 0: Data transfer from PWBFR_n to PWDTR_n is enabled
with PWCNT_n and PWCYR_n compare match
1: Data transfer from PWBFR_n to PWDTR_n is disabled
with PWCNT_n and PWCYR_n compare match
6 BTC2E 0 R/W
5 BTC2C 0 R/W
4 BTC2A 0 R/W
3 BTC1G 0 R/W
2 BTC1E 0 R/W
1 BTC1C 0 R/W
0 BTC1A 0 R/W