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Section 24 A/D Converter
R01UH0134EJ0400 Rev. 4.00 Page 1277 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(1)
(2)
Bφ
ADF
t
D
t
SPL
t
CONV
Write
signal
Input sampling
timing
(1):
(2):
t
D
:
t
SPL
:
t
CONV
:
[Legend]
Address
ADCSR write cycle
ADCSR address
A/D conversion start delay time
Input sampling time
A/D conversion time
Figure 24.5 A/D Conversion Timing