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Section 2 CPU
R01UH0134EJ0400 Rev. 4.00 Page 53 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
2.1.4 Register Banks
For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and
system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried
out using a register bank. The register contents are automatically saved in the bank after the CPU
accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a
RESBANK instruction in an interrupt processing routine.
This LSI has 15 banks. For details, see the SH-2A, SH2A-FPU Software Manual and section 7.8,
Register Banks.
2.1.5 Initial Values of Registers
Table 2.1 lists the values of the registers after a reset.
Table 2.1 Initial Values of Registers
Classification Register Initial Value
General registers R0 to R14 Undefined
R15 (SP) Value of the stack pointer in the vector
address table
Control registers SR Bits I[3:0] are 1111 (H'F), BO and CS are
0, reserved bits are 0, and other bits are
undefined
GBR, TBR Undefined
VBR H'00000000
System registers MACH, MACL, PR Undefined
PC Value of the program counter in the vector
address table