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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 335 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(11) Power-Down Mode
If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in power-down mode by bringing
the CKE signal to the low level in the non-access cycle. This power-down mode can effectively
lower the power consumption in the non-access cycle. However, please note that if an access
occurs in power-down mode, a cycle of overhead occurs because a cycle is needed to assert the
CKE in order to cancel the power-down mode.
Figure 9.29 shows the access timing in power-down mode.
TnopPower-down Tr Tc1 Td1 Tde Tap Power-down
CKIO
CKE
A25 to A0
CSn
RD/WR
RAS
DQMx
D15 to D0
BS
DACKn*
2
A12/A11*
1
CAS
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.29 Power-Down Mode Access Timing