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Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00 Page 1565 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(3) AC Modulation Signal (Alternating Signal)
This output signal is toggled between high and low (H -> L-> H -> ...) every specified number of
lines.
The interval is calculated as (set value) + 1 lines.
LCD_HSYNC
LCD_M_DISP
Line n Line n+1 Line n+2 Line n+3 Line n+4
Example: Toggled every two lines
Figure 27.13 LCD_M_DISP Signal Description
(4) Sync Signal Output Timing
The sync signal output timing is shown below.
The vertical sync signal changes in synchronization with the rising edge (the falling edge when the
output is invered) of the horizontal sync signal.
LCD_HSYNC
LCD_VSYNC
LCD_CLK
LCD_HSYNC
LCD_VSYNC
(b)
(a)
(a) Vertical sync signal pulse width (1H units) = VSYNC_END - VSYNC_START
(b) Horizontal sync signal pulse width (clock pulse units) = HSYNC_END - HSYNC_START
Figure 27.14 Sync Signal Output Timing