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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1483 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(b) When the BRDYM bit is 0 and the BFRE bit is 1
With these settings, this module generates the BRDY interrupt on completion of reading all the
data for a single transfer using the pipe in the receiving direction, and sets 1 to the PIPEBRDY bit
corresponding to the pertinent pipe.
On any of the following conditions, this module determines that the last data for a single transfer
has been received.
When a short packet including a zero-length packet is received.
When the transaction counter register (TRNCNT bits) is used and the number of packets
specified by the TRNCNT bits are completely received.
When the pertinent data is completely read out after any of the above determination conditions has
been satisfied, this module determines that all the data for a single transfer has been completely
read out.
When a zero-length packet is received while the FIFO buffer is empty, the USB 2.0 host/function
module determines that all the data for a single transfer has been read at the point at which the
FRDY bit is set to 1 and the DTLN bit cleared to 0 in the FIFO port control register. In this case,
to start the next transfer, write 1 to the BCLR bit in the corresponding FIFOCTR register.
With these settings, this module does not detect the BRDY interrupt for the pipe in the
transmitting direction.
The PIPEBRDY interrupt status of the pertinent pipe can be cleared to 0 by writing 0 to the
corresponding PIPEBRDY interrupt status bit. In this case, 1s should be written to the PIPEBRDY
interrupt status bits for the other pipes.
In this mode, the BFRE bit setting should not be modified until all the data for a single transfer has
been processed. When it is necessary to modify the BFRE bit before completion of processing, all
the FIFO buffers for the pertinent pipe should be cleared using the ACLRM bit.