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Section 6 Exception Handling
Page 140 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(3) Power-On Reset Initiated by Watchdog Timer
When a setting is made for a power-on reset to be generated in watchdog timer mode of the
watchdog timer, and WTCNT of the watchdog timer overflows, this LSI enters the power-on reset
state.
In this case, WRCSR of the watchdog timer and FRQCR of the clock pulse generator are not
initialized by the reset signal generated by the watchdog timer.
If a reset caused by the RES pin or the user debugging interface reset assert command occurs
simultaneously with a reset caused by watchdog timer overflow, the reset caused by the RES pin
or the user debugging interface reset assert command has priority, and the WOVF bit in WRCSR
is cleared to 0. When power-on reset exception processing is started by the watchdog timer, the
CPU operates in the same way as when a power-on reset was caused by the RES pin.
6.2.4 Manual Reset
(1) Manual Reset Initiated by Watchdog Timer
When a setting is made for a manual reset to be generated in watchdog timer mode of the
watchdog timer, and WTCNT of the watchdog timer overflows, this LSI enters the manual reset
state.
When manual reset exception processing is started by the watchdog timer, the CPU operates as
follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to
I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are
initialized to 0. The BN bit in IBNR of interrupt controller is also initialized to 0.
4. The values fetched from the exception handling vector table are set in the PC and SP, and the
program begins executing.