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Section 9 Bus State Controller
Page 262 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
CS6WCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
RRRRRRRRRRRR/WRRRR
0000010100000000
R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
-----------BAS----
- - - SW[1:0] WR[3:0] WM - - - - HW[1:0]
Bit Bit Name
Initial
Value
R/W Description
31 to 21
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
20 BAS 0 R/W SRAM with Byte Selection Byte Access Select
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read/write
access cycle and asserts the RD/WR signal at the
write timing.
19 to 13
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, C
S
6 Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address,
CS6 assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles