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Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00 Page 585 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(3) Underflow Interrupt
An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to
1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing
the TCFU flag to 0. This module has two underflow interrupts, one each for channels 1 and 2.
11.5.2 Activation of Direct Memory Access Controller
The direct memory access controller can be activated by the TGRA input capture/compare match
interrupt in each channel. For details, see section 10, Direct Memory Access Controller.
In this module, a total of five TGRA input capture/compare match interrupts can be used as direct
memory access controller activation sources, one each for channels 0 to 4.
11.5.3 A/D Converter Activation
The A/D converter can be activated by one of the following three methods in this module. Table
11.56 shows the relationship between interrupt sources and A/D converter start request signals.
(1) A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4
Trough in Complementary PWM Mode
The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in
each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in
TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 =
H'0000).
A/D converter start request signal TRGAN is issued to the A/D converter under either one of the
following conditions.
When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare
match on a particular channel while the TTGE bit in TIER is set to 1
When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary
PWM operation while the TTGE2 bit in TIER_4 is set to 1
When either condition is satisfied, if A/D converter start signal TRGAN from this module is
selected as the trigger in the A/D converter, A/D conversion will start.