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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 415 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
CHCR DMARS DMA Transfer
Request
Source
DMA Transfer Request Signal
Transfer
Source
Transfer
Destination
Bus
Mode
RS[3:0] MID RID
1000 100011 01
Serial
communication
interface with
FIFO
Channel 3
TXI3 (transmit FIFO data empty) Any SCFTDR_3 Cycle
steal
10 RXI3 (receive FIFO data full) SCFRDR_3 Any
100100 01
Serial
communication
interface with
FIFO
Channel 4
TXI4 (transmit FIFO data empty) Any SCFTDR_4
10 RXI4 (receive FIFO data full) SCFRDR_4 Any
100101 01
Serial
communication
interface with
FIFO
Channel 5
TXI5 (transmit FIFO data empty) Any SCFTDR_5
10 RXI5 (receive FIFO data full) SCFRDR_5 Any
100110 01
Serial
communication
interface with
FIFO
Channel 6
TXI6 (transmit FIFO data empty) Any
SCFTDR_6
10 RXI6 (receive FIFO data full) SCFRDR_6 Any
100111 01
Serial
communication
interface with
FIFO
Channel 7
TXI7 (transmit FIFO data empty) Any SCFTDR_7
10 RXI7 (receive FIFO data full) SCFRDR_7 Any
101100 11 A/D converter ADI (A/D conversion end) ADDR Any
101110 11
NAND flash
memory
controller
Data part
Transmission FIFO data empty
Any FLDTFIFO
Data part
Reception FIFO data full
FLDTFIFO Any
101111 11
Control code part
Transmission FIFO data empty
Any FLECFIFO
Control code part
Reception FIFO data full
FLECFIFO Any
110100 01 Decompression
unit
IFEI (input FIFO empty) Any Input buffer
register
10 OFFI (output FIFO full) Output
buffer
register
Any