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Section 35 Motor Control PWM Timer
Page 1838 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
PWCNT_1/2
(lower 10 bits)
PWCYR_1/2
(lower 10 bits)
PWDTR_1/2
(lower 10 bits)
PWM output on
selected pin
PWM output on
unselected pin
Compare match
01
N
M
M–2 M–1 M N–1 0
Figure 35.3 Duty Register Compare Match (OPS = 0 in PWPR_n)
01 N–1 0
N
M
N–2
PWCNT_1/2
(lower 10 bits)
PWCYR_1/2
(lower 10 bits)
PWDTR_1/2
(lower 10 bits)
PWM output
(M = 0)
PWM output
(0 < M < N)
PWM output
(N ≤ M)
Figure 35.4 Differences in PWM Output According to Duty Register Set Value
(OPS = 0 in PWPR_n)