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Section 25 NAND Flash Memory Controller
Page 1304 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
25.3.6 Data Counter Register (FLDTCNTR)
FLDTCNTR is a 32-bit readable/writable register that specifies the number of bytes to be read or
written in command access mode.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
151413121110987654321
0
0000000000000000
RRRRRRRRRRRRRRRR
0000000000000000
RRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
ECFLW[7:0]
----
DTFLW[7:0]
DTCNT[11:0]
Bit Bit Name
Initial
Value R/W Description
31 to 24 ECFLW
[7:0]
H'00 R FLECFIFO Access Count
Specify the number of longwords in FLECFIFO to be
read or written. These bit values are used when the
CPU reads from or writes to FLECFIFO.
In FLECFIFO read, these bits specify the number of
longwords of the data that can be read from FLECFIFO.
In FLECFIFO write, these bits specify the number of
longwords of unoccupied area that can be written in
FLECFIFO.
23 to 16 DTFLW
[7:0]
H'00 R FLDTFIFO Access Count
Specify the number of longwords in FLDTFIFO to be
read or written. These bit values are used when the
CPU reads from or writes to FLDTFIFO.
In FLDTFIFO read, these bits specify the number of
longwords of the data that can be read from FLDTFIFO.
In FLDTFIFO write, these bits specify the number of
longwords of unoccupied area that can be written in
FLDTFIFO.
15 to 12
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 0 DTCNT
[11:0]
H'000 R/W Data Count Specification
Specify the number of bytes of data to be read or
written in command access mode. (Up to 2048 + 64
bytes can be specified.)