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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 299 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 9.9. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw
cycle to the T2 cycle.
T1
CKIO
A25 to A0
CSn
RD/WR
RD
D15 to D0
WEn
D15 to D0
WAIT
Tw Tw
Twx T2
Read
Write
BS
Wait states inserted
by WAIT signal
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.9 Wait Cycle Timing for Normal Space Access
(Wait Cycle Insertion Using WAIT Signal)