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Section 32 General Purpose I/O Ports
R01UH0134EJ0400 Rev. 4.00 Page 1683 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 32.8 Multiplexed Pins (Port G)
Setting
Register
Setting Mode Bit (PGnMD[2:0])
000 001 010 011 100 101
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6
PGCR7 PG0 LCD_DATA0 SD_D2 PINT0 WDTOVF
PGCR6 PG24 MISO1 TIOC0D
PGCR5 PG23 MOSI1 TIOC0C
PG22 SSL10 TIOC0B
PG21 RSPCK1 TIOC0A
PG20 LCD_EXTCLK MISO1 TxD7
PGCR4 PG19 LCD_CLK TIOC2B MOSI1 RxD7
PG18 LCD_DE TIOC2A SSL10 TxD6
PG17 LCD_HSYNC TIOC1B RSPCK1 RxD6
PG16 LCD_VSYNC TIOC1A TxD3 CTS1
PGCR3 PG15 LCD_DATA15 TIOC0D RxD3 RTS1
PG14 LCD_DATA14 TIOC0C SCK1
PG13 LCD_DATA13 TIOC0B TxD1
PG12 LCD_DATA12 TIOC0A RxD1
PGCR2 PG11 LCD_DATA11 SSITxD0 IRQ3 TxD5 SIOFTxD
PG10 LCD_DATA10 SSIRxD0 IRQ2 RxD5 SIOFRxD
PG9 LCD_DATA9 SSIWS0 TxD4 SIOFSYNC
PG8 LCD_DATA8 SSISCK0 RxD4 SIOFSCK
PGCR1 PG7 LCD_DATA7 SD_CD PINT7 IRQ7*
PG6 LCD_DATA6 SD_WP PINT6 IRQ6*
PG5 LCD_DATA5 SD_D1 PINT5 IRQ5*
PG4 LCD_DATA4 SD_D0 PINT4 IRQ4*
PGCR0 PG3 LCD_DATA3 SD_CLK PINT3
PG2 LCD_DATA2 SD_CMD PINT2
PG1 LCD_DATA1 SD_D3 PINT1