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Section 10 Direct Memory Access Controller
Page 372 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Decompression unit: two sources
Selectable bus modes
Cycle steal mode (normal mode or intermittent mode)
Burst mode
Selectable channel priority levels: The channel priority levels are selectable between two fixed
modes.
Interrupt request: An interrupt request can be sent to the CPU on completion of half- or full-
data transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to
the CPU when half of the initially specified DMA transfer is completed.
External request detection: There are following four types of DREQ input detection.
Low level detection
High level detection
Rising edge detection
Falling edge detection
Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND
can be set independently.
Support of reload functions in DMA transfer information registers: DMA transfer using the
same information as the current transfer can be repeated automatically without specifying the
information again. Modifying the reload registers during DMA transfer enables next DMA
transfer to be done using different transfer information. The reload function can be enabled or
disabled independently in each channel or reload register.
Note: * Channel 1 can receive external requests only in the SH7264 Group.