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Section 10 Direct Memory Access Controller
Page 402 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
10.3.9 DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7)
The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that
specify the source of the DMA transfer request from peripheral modules in each channel.
DMARS0 to DMARS7 are for channels 0 and 1, 2 and 3, 4 and 5, 6 and 7, 8 and 9, 10 and 11, 12
and 13, and 14 and 15, respectively. Table 10.3 shows the specifiable combinations.
DMARS can specify the following transfer request sources (The following modules can issue on-
chip peripheral module requests):
Serial communication interface with FIFO: 16 sources
I
2
C bus interface 3: six sources
A/D converter: one source
Multi-function timer pulse unit 2: five sources
Compare match timer: two sources
USB 2.0 host/function module: two sources
NAND flash memory controller: two sources
Controller area network: two sources
Serial sound interface: five sources
Sampling rate converter: four sources
Renesas SPDIF interface: two sources
CD-ROM decoder: one source
SD host interface: two sources
Renesas serial peripheral interface: four sources
Clock synchronous serial I/O with FIFO: two sources
Motor control PWM timer: two sources
Decompression unit: two sources
Two transfer request sources for the controller area network do not need to be specified by these
registers, for they can be specified using the RS3 to RS0 bits in the DMA channel control register
(CHCR).