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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1033 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(4) Abort Acknowledge Register (ABACK1, ABACK0)
The ABACK1 and ABACK0 are 16-bit read/conditionally-write registers. These registers are used
to signal to the CPU that a mailbox transmission has been aborted as per its request. When an
abort has succeeded this module sets the corresponding bit in the ABACK register. The CPU may
clear the Abort Acknowledge bit by writing a '1' to the corresponding bit location. Writing a '0' has
no effect. An ABACK bit position is set by this module to acknowledge that a TXPR bit has been
cleared by the corresponding TXCR bit.
ABACK1
1514131211109876543210Bit:
Initial value:
R/W:
0000000000000000
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
ABACK1[15:0]
Note: * Only when writing a '1' to clear.
Bit 15 to 0 — Notifies that the requested transmission cancellation of the corresponding Mailbox
has been performed successfully. The bit 15 to 0 corresponds to Mailbox-31 to 16 respectively.
Bit[15:0]:ABACK1 Description
0 [Clearing Condition] Writing '1' (Initial value)
1 Corresponding Mailbox has cancelled transmission of message (Data or
Remote Frame)
[Setting Condition]
Completion of transmission cancellation for corresponding mailbox
ABACK0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit:
Initial value:
R/W:
-
0
R
000000000000000
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
ABACK0[15:1]
Note: * Only when writing a '1' to clear.
Bit 15 to 1 — Notifies that the requested transmission cancellation of the corresponding Mailbox
has been performed successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.