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Section 28 Sampling Rate Converter
Page 1662 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(1) When Interrupts are Issued to CPU
1. Set the OEN bit in SRCODCTRL to 1.
2. When the OINT bit in SRCSTAT is set to 1, the ODF interrupt request is issued. In the
interrupt processing routine, read the OINT bit and confirm that it is 1, read data from
SRCOD, and write 0 to the OINT bit. Then return from the interrupt processing routine.
3. After flush processing starts, repeat step 2 until the CEF bit in SRCSTAT is read as 1.
(2) When Interrupts are Used to Activate Direct Memory Access Controller
1. Assign ODFI of this module to one channel of the direct memory access controller.
2. Set the OEN bit in SRCODCTRL to 1.
3. When the OINT bit in SRCSTAT is set to 1, the ODF interrupt request is issued thus activating
the direct memory access controller. When the direct memory access controller has read data
from SRCOD thus resulting in the number of data units in the output data FIFO being less than
the triggering number specified by the OFTRG1 and OFTRG0 bits in SRCODCTRL, the
OINT bit is cleared to 0.
4. After flush processing starts, repeat step 3 until the FLF bit in SRCSTAT is read as 0.
(3) When Serial Sound Interface Interrupts are Used for Activating Direct Memory Access
Controller to Transfer Output Data to Serial Sound Interface
1. Set the OVEN bit in SRCCTRL to 0 to disable the OVF interrupt request generation.
2. Assign the serial sound interface to one channel of the direct memory access controller as a
DMA transfer request source. Set SRCID of the sampling rate converter as a transfer source
and SSIFTDR of the serial sound interface as a transfer destination, and set the serial source
interface to enable transmission operation.
3. When the TDE bit in SSIFSR is set to 1, the serial sound interface issues an interrupt request
thus activating the direct memory access controller. The direct memory access controller then
reads data from SRCOD and writes the data to SSIFTDR.
4. After flush processing starts, repeat step 3 until the CEF bit in SRCSTAT is read as 1.