Renesas R5S72643 Doll User Manual


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Page xxii of xl R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
16.3.5 Data Register (SPDR) ....................................................................................... 789
16.3.6 Sequence Control Register (SPSCR) ................................................................ 790
16.3.7 Sequence Status Register (SPSSR) ................................................................... 792
16.3.8 Bit Rate Register (SPBR) ................................................................................. 793
16.3.9 Data Control Register (SPDCR) ....................................................................... 795
16.3.10 Clock Delay Register (SPCKD) ........................................................................ 797
16.3.11 Slave Select Negation Delay Register (SSLND) .............................................. 798
16.3.12 Next-Access Delay Register (SPND) ............................................................... 799
16.3.13 Command Register (SPCMD) .......................................................................... 800
16.3.14 Buffer Control Register (SPBFCR) .................................................................. 805
16.3.15 Buffer Data Count Setting Register (SPBFDR) ................................................ 807
16.4 Operation .......................................................................................................................... 808
16.4.1 Overview of Operations .................................................................................... 808
16.4.2 Pin Control ........................................................................................................ 809
16.4.3 System Configuration Example ........................................................................ 810
16.4.4 Transfer Format ................................................................................................ 813
16.4.5 Data Format ...................................................................................................... 815
16.4.6 Error Detection ................................................................................................. 827
16.4.7 Initialization ...................................................................................................... 832
16.4.8 SPI Operation .................................................................................................... 833
16.4.9 Error Handling .................................................................................................. 846
16.4.10 Loopback Mode ................................................................................................ 847
16.4.11 Interrupt Sources ............................................................................................... 848
Section 17 I
2
C Bus Interface 3 ........................................................................... 849
17.1 Features ............................................................................................................................. 849
17.2 Input/Output Pins .............................................................................................................. 851
17.3 Register Descriptions ........................................................................................................ 852
17.3.1 I
2
C Bus Control Register 1 (ICCR1) ................................................................. 853
17.3.2 I
2
C Bus Control Register 2 (ICCR2) ................................................................. 856
17.3.3 I
2
C Bus Mode Register (ICMR) ........................................................................ 858
17.3.4 I
2
C Bus Interrupt Enable Register (ICIER) ....................................................... 860
17.3.5 I
2
C Bus Status Register (ICSR) ......................................................................... 862
17.3.6 Slave Address Register (SAR) .......................................................................... 865
17.3.7 I
2
C Bus Transmit Data Register (ICDRT) ........................................................ 865
17.3.8 I
2
C Bus Receive Data Register (ICDRR) .......................................................... 866
17.3.9 I
2
C Bus Shift Register (ICDRS) ........................................................................ 866
17.3.10 NF2CYC Register (NF2CYC) .......................................................................... 867
17.4 Operation .......................................................................................................................... 868
17.4.1 I
2
C Bus Format .................................................................................................. 868
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