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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1045 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(4) Timer Status Register (TSR)
This register is a 16-bit read-only register, and allows the CPU to monitor the Timer Compare
Match status and the Timer Overrun Status.
TSR (Address = H'088)
1514131211109876543210
0000000000000000
RRRRRRRRRRRRRRRR
TSR4 TSR3 TSR2 TSR1 TSR0
Bit:
Initial value:
R/W:
--------- --
Bits 15 to 5: Reserved. The written value should always be '0' and the returned value is '0'.
Bit 4 to 0 — Timer Status (TSR[4:0]): This read-only field allows the CPU to monitor the status
of the Cycle Counter, the Timer and the Compare Match registers. Writing to this field has no
effect.
Bit 4 — Start of New System Matrix (TSR4): Indicates that a new system matrix is starting.
When CCR = 0, this bit is set at the successful completion of reception/transmission of time
reference message.
Bit4: TSR4 Description
0 A new system matrix is not starting (initial value)
[Clearing condition] Writing '1' to IRR10 (Cycle Counter Overflow Interrupt)
1 Cycle counter reached zero
[Setting condition]
When the Cycle Counter value changes from the maximum value (CMAX) to
H'0. Reception/transmission of time reference message is successfully
completed when CMAX!= 3'b111 and CCR = 0