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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 267 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
21, 20 BST[1:0] 00 R/W Burst Count Specification
Specify the burst count for 16-byte access. These bits
must not be set to B'11, because B'11 setting is
reserved.
Bus Width BST[1:0] Burst count
8 bits 00 16 burst one time
01 4 burst four times
16 bits 00 8 burst one time
01 2 burst four times
10 4-4 or 2-4-2 burst
19, 18 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or subsequent access cycles in
burst access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 13 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CS4 assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles