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Section 5 Clock Pulse Generator
R01UH0134EJ0400 Rev. 4.00 Page 117 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
The blocks of this module function as follows:
(1) Crystal Oscillator
The crystal oscillator is used in which the crystal resonator is connected to the XTAL/EXTAL pin
or USB_X1/USB_X2 pin. One of them is selected according to the clock operating mode.
(2) Divider 1
Divider 1 divides the output from the crystal oscillator or the external clock input. The division
ratio depends on the clock operating mode.
(3) PLL Circuit
PLL circuit multiplies the frequency of the output from the divider 1. The multiplication ratio
depends on the clock operating mode.
(4) Divider 2
Divider 2 generates a clock signal whose operating frequency can be used for the CPU clock, the
peripheral clock, and the bus clock. The division ratio of the bus clock depends on the clock
operating mode. The division ratio of the CPU clock and the peripheral clock is set by the
frequency control register.
(5) Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the MD_CLK0 and
MD_CLK1 pins and the frequency control register (FRQCR).
(6) Standby Control Circuit
The standby control circuit controls the states of the on-chip oscillation circuit and other modules
during clock switching, or sleep, software standby or deep standby mode.
In addition, the standby control register is provided to control the power-down mode of other
modules. For details on the standby control register, see section 33, Power-Down Modes.
(7) Frequency Control Register (FRQCR)
The frequency control register (FRQCR) has control bits assigned for the following functions:
clock output/non-output from the CKIO pin during software standby mode and the frequency
division ratio of the CPU clock and the peripheral clock (P).