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Section 9 Bus State Controller
Page 292 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 9.5 16-Bit External Device Access and Data Alignment in Big Endian
Data Bus Strobe Signals
Operation D15 to D8 D7 to D0 WE1, DQMU WE0, DQML
Byte access at address 0 Data 7 to 0 Assert
Byte access at address 1 Data 7 to 0 Assert
Byte access at address 2 Data 7 to 0 Assert
Byte access at address 3 Data 7 to 0 Assert
Word access at address 0 Data 15 to 8 Data 7 to 0 Assert Assert
Word access at address 2 Data 15 to 8 Data 7 to 0 Assert Assert
Longword
access at
address 0
1st access at address 0 Data 31 to 24 Data 23 to 16 Assert Assert
2nd access at address 2 Data 15 to 8 Data 7 to 0 Assert Assert
Table 9.6 8-Bit External Device Access and Data Alignment in Big Endian
Data Bus Strobe Signals
Operation D15 to D8 D7 to D0 WE1, DQMU WE0, DQML
Byte access at address 0 Data 7 to 0 Assert
Byte access at address 1 Data 7 to 0 Assert
Byte access at address 2 Data 7 to 0 Assert
Byte access at address 3 Data 7 to 0 Assert
Word
access at
address 0
1st access at address 0 Data 15 to 8 Assert
2nd access at address 1 Data 7 to 0 Assert
Word
access at
address 2
1st access at address 2 Data 15 to 8 Assert
2nd access at address 3 Data 7 to 0 Assert
Longword
access at
address 0
1st access at address 0 Data 31 to 24 Assert
2nd access at address 1 Data 23 to 16 Assert
3rd access at address 2 Data 15 to 8 Assert
4th access at address 3 Data 7 to 0 Assert