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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 337 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Setting for Area 3
Burst read/single write (burst length 1):
Data Bus Width CAS Latency Access Address External Address Pin
16 bits 2 H'FFFC5440 H'0000440
3 H'FFFC5460 H'0000460
Burst read/burst write (burst length 1):
Data Bus Width CAS Latency Access Address External Address Pin
16 bits 2 H'FFFC5040 H'0000040
3 H'FFFC5060 H'0000060
Mode register setting timing is shown in figure 9.30. A PALL command (all bank pre-charge
command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An
MRS command (mode register write command) is finally issued. Idle cycles, of which number is
specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the
first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR,
are inserted between REF and REF, and between the 8th REF and MRS. One or more idle cycles
are inserted between the MRS and a command to be issued next.
It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after
power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse
width of the reset signal is longer than the idle time, mode register setting can be started
immediately after the reset, but care should be taken when the pulse width of the reset signal is
shorter than the idle time.