Filter
Top Products
Section 20 Controller Area Network
Page 1066 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Watch_Trigger
TCMR2
<Configuration> Cycle Time varies between L and Time_Ref + L
Slave
Cycle Time = 0 = L
Cycle Time
= Time_Ref
= Time_Ref + L
CCR = 1
CCR = 0
CCR = 0
capture timestamp
at SOF of reception
Ref_Mark and CCR are updated
at successful end of time reference reception
= Time_Ref + L= Time_Ref
Time_Mark 1
TTT in MB24
Time_Mark 2
TTT in MB25
Time_Mark 3
TTT in MB26
Time_Mark 4
TTT in MB27
Time_Mark 5
TTT in MB28
Time_Mark 6
TTT in MB29
Time_Ref
TTT in MB30
Time_Mark 1
TTT in MB24
Time_Mark 2
TTT in MB25
Time_Mark 3
TTT in MB26
Time_Mark 4
TTT in MB27
Time_Mark 5
TTT in MB28
Time_Mark 6
TTT in MB29
Time_Ref
TTT in MB30
Time_Mark 1
TTT in MB24
Time_Mark 2
TTT in MB25
Time_Mark 3
TTT in MB26
Time_Mark 4
TTT in MB27
Time_Mark 5
TTT in MB28
Time_Mark 6
TTT in MB29
Time_Ref
TTT in MB30
CCR isn't incremented unlike time mastercopy CCR from received time reference
<Normal Operation>
L
Figure 20.20 Time Slave
Function to be implemented by software
Some of the TTCAN functions need to be implemented in software. The main details are reported
hereafter. Please refer to ISO-11898-4 for more details.
Change from Init_Watch_Trigger to Watch_Trigger
This module offers the two registers TCMR0 and TCMR2 as H/W support for
Init_Watch_Trigger and Watch_Trigger respectively. The SW is requested to enable
TCMR0 and disable TCMR2 up to the first reference message is detected on the CAN Bus
and then disable TCMR0 and enable TCMR2.- Schedule Synchronization state machine.
Only reception of Next_is_Gap interrupt is supported. The application needs to take care of
stopping all transmission at the end of the current basic cycle by setting the related TXCR
flags.Master-Slave Mode control.
Only automatic cycle time synchronization and CCR increment is supported.
Message status count
Software has to count scheduling errors for periodic messages in exclusive windows.